Currently, high-speed circuitry capable of utilizing signals having frequencies of greater than or equal to one GHz is of increasing interest. After manufacturing of the high-speed circuitry is completed, it is highly desirable to test the circuitry to ensure that it functions properly. For example, high-speed mixed signal phase and clock recovery circuits, such as used in serializer/deserializer (SERDES) circuits, often run at several GHz. SERDES circuitry use phase and clock recovery circuits, such as a phase locked loop, to recover the clock from a high-speed serial signal input to the SERDES. Using the recovered clock as well as the data from the serial signal, a serializing/deserializing block of the SERDES can convert the serial signal to a parallel signal. The high-speed mixed signal phase and clock recovery circuits, as well as the remainder of the SERDES, are tested prior to delivery to a customer to ensure that the circuitry operates substantially as desired. Without such testing, the products delivered to the customer could contain errors, causing an additional expenditure of resource on the part of both the customer and the manufacturer of the high-speed circuits.
A conventional tester could be used to test high-speed signals such as high-speed mixed signal phase and clock recovery circuits. When operated in a conventional manner, the conventional tester would input a signal to the high-speed mixed signal phase and clock recovery circuit under test. The signal could have a particular frequency as well as a delay corresponding to a phase change. The output of the high-speed mixed signal phase and clock recovery circuit under test could then be observed to determine whether the high-speed mixed signal phase and clock recovery circuit functions as desired.
Although conventional testers could be used to test the high-speed circuitry, one of ordinary skill in the art will readily recognize that conventional testers do not run at frequencies greater than one GHz and may not set the absolute delay between signals with a high degree of accuracy. As such, the signal provided by the conventional tester is significantly lower than the frequencies at which the high-speed circuitry can operate. Consequently, conventional testers operated in a conventional manner are unable to verify that the high frequency operation of the high-speed mixed signal phase and clock recovery circuits mentioned above is without functional errors.
Other conventional methods can test the high frequency operation of the high-speed mixed signal phase and clock recovery circuit. For example, a specialized tester capable of outputting signals of greater than one GHz with an accurate delay could be provided. However, the cost of such a tester would be significant.
FIG. 1 depicts the conventional high-speed circuit 10 being tested using a conventional tester 20. This conventional method 10 for testing the operation of high-speed mixed signal phase and clock recovery circuits employs specialized boundary scan latches. The conventional high-speed circuit 10 thus includes boundary scan latches 12, switching circuitry 14, phase and clock recovery circuitry 16. Thus, the conventional high-speed circuit 10 shown could be part of SERDES circuitry. In such a case, the conventional high-speed circuit 10 could be coupled to a serializing/deserializing block (not shown). The switching circuitry 14 allows the boundary scan latches 12 to be switched between test and normal operation modes. During testing, the boundary scan latches 14 of the high-speed mixed signal phase and clock recovery circuit 10 are switched to a test mode. In test mode, the boundary scan latches 12 can be used in conjunction with the conventional tester 20 to examine the high frequency behavior of the high-speed circuitry 10.
Although the conventional high-speed circuit 10 can be tested using the conventional tester 20, one of ordinary skill in the art will readily recognize that the specialized boundary scan latches 12 would also require the use of special topologies in the conventional high-speed circuit 10. Furthermore, the switching circuits 14 that permit the boundary scan latches 12 to switch between the test and normal operation modes consume additional power. The switching circuits 14 may also result in a lower operating frequency of the conventional high-speed circuitry 10 due to the additional capacitive load on the high-speed phase and clock recovery circuitry 16. The additional power consumption and lower operating frequency are both undesirable in high-speed circuits.
Accordingly, what is needed is a system and method for testing of high-speed circuitry such as high-speed mixed signal phase and clock recovery circuits. The present invention addresses such a need.